A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation

We present a 3.5 GHz fractional-N ADPLL with a 3.4 MHz bandwidth operating from a 35 MHz reference. Using a dithering algorithm and feedforward compensation around the TDC results in spurious performance better than -58 dBc, and in-band phase noise of -101 dBc/Hz. The IC with fully integrated calibration logic occupies 0.44 mm ² in 65 nm CMOS, and consumes 8.7 mW.