Reliability Simulation Analysis of TSV Structure in Silicon Interposer under Temperature Cycling

通过硅通孔 可靠性(半导体) 中间层 温度循环 材料科学 自行车 可靠性工程 电子工程 光电子学 工程类 复合材料 物理 热力学 历史 功率(物理) 蚀刻(微加工) 考古 图层(电子) 热的
作者
Wenchao Tian,H. Dang,Dexin Li,Yunhao Cong,Yuanming Chen
出处
期刊:Micromachines [Multidisciplinary Digital Publishing Institute]
卷期号:15 (8): 986-986
标识
DOI:10.3390/mi15080986
摘要

As semiconductor integration scales expand and chip sizes shrink, Through Silicon Via (TSV) technology advances towards smaller diameters and higher aspect ratios, posing significant challenges in thermo-mechanical reliability, particularly within interposer substrates where mismatched coefficients of thermal expansion exacerbate issues. This study conducts a thermo-mechanical analysis of TSV structures within multi-layered complex interposers, and analyzes the thermal stress behavior and reliability under variable temperature conditions (-55 °C to 85 °C), taking into account the typical electroplating defects within the copper pillars in TSVs. Initially, an overall model is established to determine the critical TSV locations. Sub-model analysis is then employed to investigate the stress and deformation of the most critical TSV, enabling the calculation of the temperature cycle life accordingly. Results indicate that the most critical TSV resides centrally within the model, exhibiting the highest equivalent stress. During the temperature cycling process, the maximum deformation experiences approximately periodic variations, while the maximum equivalent stress undergoes continuous accumulation and gradually diminishes. Its peak occurs at the contact interface corner between the TSV and Redistribution Layer (RDL). The estimated life of the critical point is 3.1708 × 105 cycles. Furthermore, it is observed that electroplating defect b alleviates thermal stress within TSVs during temperature cycling. This study provides insights into TSV thermal behavior and reliability, which are crucial for optimizing the design and manufacturing processes of advanced semiconductor packaging.
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