A Design of Low Power and Small Area 8 bit 200KS/s Synchronous Single-Ended SAR ADC

This paper presents a design of low power 8 bit 200KS/s Synchronous Successive Approximation Register analog to digital (SAR ADC) converter. The proposed architecture is composed of Input Buffer, Dynamic Latch Comparator, Capacitive DAC, Reference Voltage Generator, and SAR Logic. Dynamic latch comparator is used to reduce the leakage current. In order to implement low power, the architecture of SAR ADC has been used and medium resolution among the architectures. The proposed structure is designed using 55-nm Complementary Metal-Oxided-Semiconductor (CMOS) process technology with 1V of supply voltage and 781.2 Hz of input frequency. The results of the architecture are achieved an effective number of bits (ENOB) of 7.997 bits and a signal to noise, distortion ration (SNDR) level of 49.899 dB with sampling rate 200KS/s. Furthermore, total power consumption of the structure is 245 uW.