Die-to-wafer hybrid bonding (D2W HB) is a promising technology that requires a multi-step process to create a reliable bond between the top component die and the bottom substrate wafer. However, several important challenges must be overcome to ensure successful integration. One of the main challenges is effectively pre-treating the chiplets sourced from singulated wafers through dicing techniques. These chiplets are attached to stainless-steel frames using plastic tapes, which presents unique challenges for the D2W HB. To achieve high surface energy and void-free bonding, it is important to carefully select plasma sources and conditions to minimize organic compound re-deposition on dielectric or Copper (Cu) surfaces. In addition, high-precision chiplet placement is essential to ensure optimal die-to-wafer or die-to-die alignment. The optimization of each of the process steps and the understanding of the queue time effect between them is crucial to enabling next-generation high-performance computing (HPC) with over 20 chiplets per module or high bandwidth memory (HBM) of over 16 layers of die stacking.