Properties of isolation liner and electrical characteristics of high aspect ratio TSV in 3D stacking technology

As semiconductor performance improvements through device scale-down becomes more difficult, 3D chip stacking technology with TSVs (Through Silicon Via) is becoming an increasingly attractive solution to achieve higher system performances by way of higher bandwidth, smaller form factor and lower power consumption. Such increase in performance using TSV aided 3D chip stacking technology applies not only to homogenous chip stacking but to heterogeneous chip stacking (e.g. memory device on logic) as well, making it ideal for such applications in high performance mobile devices.