比较器
CMOS芯片
电子工程
噪音(视频)
块(置换群论)
电气工程
电压
计算机科学
还原(数学)
模数转换器
降噪
工程类
数学
人工智能
几何学
图像(数学)
作者
Patrícia Figueiredo,J.C. Vital
出处
期刊:IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing
[Institute of Electrical and Electronics Engineers]
日期:2006-07-01
卷期号:53 (7): 541-545
被引量:269
标识
DOI:10.1109/tcsii.2006.875308
摘要
The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.
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