Vertical Silicon capacitors integration within IC package for lower ESL using thicker and multiple wiring pattern

Integration within the IC package is a major challenge to solve for IC makers. The more integrated and the more functions each package has, the higher the added value for the customers. Then, an IC maker may see an interest in integrating several functions as close as possible to the active part, especially if enabling better performances without extending too much the package size. Decoupling capacitors are a good candidate for such package optimization. Decoupling capacitors can be miniaturized, optimized to be placed close to the IC and exist as vertical components to be directly wire-bonded close to the IC, inside its package. We can analyze how vertical Silicon capacitors (Si-caps) differentiate from the two other technologies that co-exist as vertical capacitors, Multi-Layer Ceramic Capacitors (MLCC) and Single-Layer Capacitors (SLC), from a packaging prospective and may improve Equivalent Series Inductance (ESL) management in dedicated IC package through wiring pattern optimization.