A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

This article proposes an analytic charge-based model that incorporates interface trapping. The model’s applicability to all operating zones includes various interface trap charges with varying doping concentrations. Using the analytical model, the impact of interface traps on different electrical parameters, such as channel potential, surface potential, electric field, and drain current, is examined. The transconductance and cut-off frequency models are also developed from the drain current model. To validate our model, the analytical model results were compared with the TCAD device simulation results and available experimental data from literature. The Fermi level location of interface traps greatly influences surface potential in the bandgap, leading to subthreshold deterioration and flat band shifting in Junction Less Field Effect Transistor (GAAJLFET) with SiO 2 as a gate insulator, which leads to performance degradation of different device parameters. To decrease the impact of the interface trap on the device’s characteristics without impairing the performance, a suitable device with SiO 2 and high-k gate-stack as an insulator is designed and compared with GAAJLFET with SiO 2 as a gate insulator. A GAAJLFET with SiO 2 as an insulating material has very different device parameters than a GAAJLFET with SiO 2 and high-k gate-stack as a gate insulating material.