Investigation of PMOS Transistor Threshold Voltage Shift in BCD Technology

A new failure mechanism of P-channel metal oxide semiconductor (PMOS) transistor threshold voltage (Vth) shift due to unintentional N-type doping onto silicon wafer from wafer fab environment, which occurred after Nanospray wet cleaning and just before oxidation, was investigated. Electrical Failure Analysis (EFA) was used to provide a reasonable explanation for the PMOS Vth shift. The doping profile of the affected PMOS transistor was successfully derived from Capacitance-Voltage (C-V) measurement, which allowed us to compare the silicon surface N-type doping concentration below the gate oxide between affected and reference samples. Numerous experiments were conducted to gather evidence supporting the hypothesis that unintentional N-type doping, transported from wafer fab environment onto the silicon wafer, causes the observed Vth shift. We implemented an effective corrective action to eliminate the risk of Vth shift, by removing affected wet cleaning process right before oxidation from affected process routes.