A 7 GHz ERBW 1.1 GS/s 6-bit PVT Tolerant Asynchronous Charge-Injection SAR With Only 8.5 fF Input Capacitance in 28 nm CMOS

This article presents a 6-bit 1.1 GS/s asynchronous charge-injection SAR (ci-SAR) analog-to-digital-converter (ADC) achieving an unprecedented area efficiency of 0.0048 GS/s/ $\mu$ m $^{2}$ per slice. A current-reduced charge injection cell (CIC) enables a small input capacitance of 8.5 fF, which helps extend the effective resolution bandwidth (ERBW) to 7 GHz. A replica-based feedback loop desensitizes the full-scale variations on process, voltage, and temperature (PVT) conditions. A common-mode shifting scheme relaxes the dynamic offset issue of the comparator inherent in monotonic switching. The chip is fabricated in a 28 nm CMOS process with an active area of 227 $\mu$ m $^{2}$ . The peak SNDR is 35.2 dB with FOM $_{\text{w}}$ $=$ 25.5 fJ/conv.-step. The measured SNDR drops by less than 2.32 dB over $-$ 40 $^{\circ}$ C to 100 $^{\circ}$ C temperature variation and 0.9 to 1.1 V supply variation.