Design and Process Simulation on High Voltage VDMOS

A VDMOS cell structure based on semiconductor physics and relevant states were designed. The process parameters of the high-voltage VDMOS have been calculated and ajusted. Using the optimal device’ dimensions, the doping concentration was ananlyzed systematically. Additionally, a simulating model of VDMOS was compiled based on SENTAURUS PROCESS. According to this model simulation, an optimized device parameters’ design was further determined. Finnally, the device drain-source breakdown voltage has satisfied a standard value of 1200V. Whereas its threshold voltage is 3.9V, which is in the prerequisite range of 3~ 5V.