Avalanche Transient Simulations of SPAD integrated in 28nm FD-SOI CMOS Technology

This article presents a study of Single Photon Avalanche Diodes (SPAD) implemented in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology based on transient TCAD simulations. The integration of SPAD in this technology is currently being studied. This work allows for a better understanding of the mechanism behind the quite high Dark Count Rate (DCR) measured at relative low excess bias voltages with the previous FD-SOI SPAD design. In this study, TCAD transient simulation methodology is introduced to better understand SPAD behavior during the avalanche process. TCAD simulations revealed that Shallow Trench Isolation (STI) structures in the active area have a negative effect on avalanche quenching, because of slower carrier evacuation with possible occurrence of secondary avalanches in series. Based on this analysis, we propose a new SPAD architecture to achieve a lower DCR.