Verification of SerDes Design Using UVM Methodology

There has always been a need to transmit data since the computer’s inception. When data is sent out of the network, it will require cable sizes to carry the data. To ease the data transmission protocols, cabling scheme, and serial communication was introduced. Numerous issues arise while transmitting data parallely such as skew, cross talk, cost and board space of System On Chip (SOC). Hence SerDes can be a great solution in moving large data from point A to Point B within the system, between two different systems or indeed between systems in different places. SerDes allows data to be transmitted at a higher rate and is less expensive. In this paper, design and verification of SerDes has been proposed. Verilog HDL was used in the design of SerDes and verification was carried out using Universal Verification Methodology (UVM) as it provides a reusable test bench and hence significantly reducing time to market.