A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS

This article presents a pulse-amplitude-modulated (PAM)-8 wireline transceiver with receiver-side pulsewidth-modulated (PWM) or time-domain-based feedforward equalization (FFE) technique. The receiver converts the voltage-modulated signals or PAM signals into PWM signals and processes them using inverter-based delay elements having a rail-to-rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 to 39.6 Gb/s and compensates 14-dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65-nm CMOS.