Linear conductance update improvement of CMOS-compatible second-order memristors for fast and energy-efficient training of a neural network using a memristor crossbar array

记忆电阻器 横杆开关 记忆晶体管 CMOS芯片 电导 人工神经网络 电阻随机存取存储器 神经形态工程学 计算机科学 能量(信号处理) 电子工程 材料科学 电气工程 物理 工程类 人工智能 电压 凝聚态物理 量子力学
作者
See‐On Park,Taehoon Park,Hakcheon Jeong,Seokman Hong,Seokho Seo,Yunah Kwon,Jongwon Lee,Shinhyun Choi
出处
期刊:Nanoscale horizons [The Royal Society of Chemistry]
卷期号:8 (10): 1366-1376 被引量:7
标识
DOI:10.1039/d3nh00121k
摘要

Memristors are two-terminal memory devices that can change the conductance state and store analog values. Thanks to their simple structure, suitability for high-density integration, and non-volatile characteristics, memristors have been intensively studied as synapses in artificial neural network systems. Memristive synapses in neural networks have theoretically better energy efficiency compared with conventional von Neumann computing processors. However, memristor crossbar array-based neural networks usually suffer from low accuracy because of the non-ideal factors of memristors such as non-linearity and asymmetry, which prevent weights from being programmed to their targeted values. In this article, the improvement in linearity and symmetry of pulse update of a fully CMOS-compatible HfO2-based memristor is discussed, by using a second-order memristor effect with a heating pulse and a voltage divider composed of a series resistor and two diodes. We also demonstrate that the improved device characteristics enable energy-efficient and fast training of a memristor crossbar array-based neural network with high accuracy through a realistic model-based simulation. By improving the memristor device's linearity and symmetry, our results open up the possibility of a trainable memristor crossbar array-based neural network system that possesses great energy efficiency, high area efficiency, and high accuracy at the same time.

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