A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

This work presents a low-spur and low-jitter fractional-N digital phase-locked loop (PLL). To reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC), two novel solutions are introduced. First, the inverse-constant-slope DTC achieves high-linearity, thanks to its immunity to channel-length modulation and non-linear parasitic capacitances. Second, the frequency-control-word (FCW) sub-tractive dithering technique randomizes the quantization error of the ?S modulator driving the PLL divider ratio without requiring an increased DTC dynamic range and pushing the fractional spurs outside the PLL bandwidth. The prototype, implemented in a 28-nm CMOS process, has an active area of 0.33 mm(2) and dissipates 17.2 mW. At fractional-N channels near 9.25 GHz, the measured in-band fractional spurs and the rms jitter are below -70 dBc and 77 fs, respectively, leading to a jitter-power figure of merit of -249.9 dB.