A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC

This paper introduces a discrete-time delta-sigma ADC for the Internet of Things (IoT) applications. It utilizes second-order 4-bit successive approximation register (SAR) quantizer architecture based on the oversampling technique to ensure a sufficiently high SQNR. Additionally, dynamic weighted averaging (DWA) technique is employed to achieve good feedback CDAC linearity. System-level analysis and circuit implementation analysis are introduced in detail. The implemented prototype of this architecture is manufactured using a 180 nm CMOS process. The proposed ADC, operating at a supply voltage of 1.8 V and a sampling frequency of 2.5 MHz, including biasing circuitry, consumes a total power of 1.3 mW. This ADC achieves a DR of 102.6 dB, SNR of 101.5 dB, and SNDR of 98.6 dB within a 10 kHz bandwidth. As a result, the Schreier figure-of-merits (FoM) for SNR, SNDR and DR is 167.46 dB, 170.36 dB, and 171.46 dB.