140-GHz 2-D Scalable On-Grid 8⨉ 8-Element Transmit–Receive Phased Arrays With Up/Down Converters Demonstrating a 5.2-m Link at 16 Gbps

This article presents a 140-GHz 2-D scalable wafer-scale transmit-receive (TRX) phased array based on radio frequency (RF) beamforming with 4-bit for both phase and gain controls. The chip is composed of $8\times8$ RF channels each having transmit and receive circuits, in addition to a TRX single-pole double-throw (SPDT) switch. One of the elements is replaced with an up/down-converter (UDC) channel composed of mixers, a $\times$ 6 LO multiplier chain, and intermediate frequency (IF) amplifiers at 9–14 GHz. The on-chip UDC channel is the interface between the IF signals on a printed circuit board (PCB) and the TX/RX RF distribution networks (DNs) on a chip. The 140-GHz DN is composed of coplanar waveguide (CPW) lines, Wilkinson dividers/combiners, and line amplifiers (LAs) to provide signal amplification. The chip occupies an area of 9.84 $\times$ 8.27 $\text{mm}^2$ and is designed and fabricated in GlobalFoundries, Malta, NY, USA, CMOS 45RFSOI technology. The chip is flipped on a low-cost organic RF PCB containing $8\times8$ patch antenna array placed at 1. $07\times1$ .22 $\text{mm}^2$ grid (0.5 $\lambda$ $\times$ 0.57 $\lambda$ at 140 GHz). The array electronically scans up to $\pm$ 60 $^{\circ}$ in the $H$ -plane and $\pm$ 38 $^{\circ}$ in the $E$ -plane for both TX and RX operations. Over-the-air (OTA) measured performance of the array demonstrates TX peak effective isotropic radiated power (EIRP) of 34-37.5 dBm at 137.5-145 GHz and RX input 1-dB compression point (P1dB) of $-$ 12 to $-$ 9 dBm at 134–143 GHz. Communication link measured for both TX and RX operations supports modulated 16-/64-quadrature amplitude modulation (QAM) signals with up to 24 Gb/s data rates with an rms EVM less than 7%/6%. In addition, a TRX phased array wireless links at 1.45 m and 5.2 meters are demonstrated with data rates up to 20 and 16 Gb/s using 16-QAM modulated signal and an rms EVM less than 9% for the 1.45 m link. To the best of the authors' knowledge, this article presents the highest reported EIRP of 37.5 dBm for wafer-scale arrays in silicon technologies.