A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity

MOSFET 碳化硅 电气工程 热阻 材料科学 结温 模具(集成电路) 光电子学 晶体管 功率MOSFET 集成电路 功率(物理) 热的 计算机科学 电压 工程类 物理 纳米技术 复合材料 气象学 量子力学
作者
Jack Knoll,Christina DiMarino,Hannes Stahr,Mike Morianz
出处
期刊:IEEE open journal of power electronics [Institute of Electrical and Electronics Engineers]
卷期号:4: 549-560 被引量:1
标识
DOI:10.1109/ojpel.2023.3293729
摘要

This paper presents a printed circuit board (PCB) -embedded 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) half-bridge package for a 22 kW electric vehicle (EV) on-board charger (OBC). The package meets the application's thermal and electrical requirements while eliminating or reducing factors that drive up manufacturing complexity and footprint in PCBs. Factors such as integration necessity, trace width, and layer count are considered. The package has been prototyped and subjected to electrical and thermal characterization. Static characterization performed on the package prototypes has revealed that the package contributes approximately 0.4 mΩ of parasitic resistance to the power loop. The simulated minimum power-loop and gate-loop inductances of the final package are 2.4 nH and 1.6 nH, respectively. Double pulse tests (DPTs) performed on the final package at 800 V and 25 A revealed that the low loop inductances allow the high-side and low-side switches to achieve 41 V/ns and 37 V/ns turn-off dv/dts , respectively, with drain-to-source voltage (VDS) overshoots of 34 V and 30 V, respectively. The selection of a non-isolated case, along with other design choices, has helped limit the junction-to-case thermal resistance (RTH,JC) of each MOSFET to 0.074 K/W.

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