共栅
噪声系数
低噪声放大器
CMOS芯片
放大器
电气工程
电感器
电子工程
PMOS逻辑
晶体管
线性
拓扑(电路)
材料科学
计算机科学
工程类
电压
作者
Priyanka Saini,C. Periasamy,Himanshu Saini,Naveen Bhushan Sharma
标识
DOI:10.1109/ic3sis54991.2022.9885380
摘要
A highly linear Low Noise Amplifier (LNA) with modified cascode topology designed at centre frequency of 2.45GHz for Wireless Local Area Network (WLAN) applications. The LNA has been designed using Cadence Virtuoso ADE with GPDK 45 nm process technology. To boost maximum stable gain (MSG), minimise noise figure, improve stability and reducing the size of the inductors, a modified cascode topology, which employed dual Common source transistors in parallel, is used. An inter modulation distortion (IMD) sink approach improves the linearity factor of LNA. This modified cascode LNA with PMOS IMD sinker has a power gain (S21) of 16.84 dB, input return loss (Sil) of -16.74 dB, Reverse isolation (S12) of -45.78 dB,Noise Figure (NF) of 0.86 dB, 1 dB compression point (PldB) of -10.6 dBm and a DC power dissipation of 1.96 mW from a power supply of IV.
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