Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration

This article presents a fractional- ${N}$ digital multiplying delay-locked loop (MDLL) that uses a digital-to-time converter (DTC) for controlling the reference injection timing to support the fractional- ${N}$ operation. This fractional- ${N}$ MDLL features an injection-error scrambling scheme for DTC error randomization and a background third-order DTC delay equalizer for DTC error calibration, to mitigate reference-injection-induced spurs while keeping a low phase noise floor. The MDLL prototype demonstrates 800-fs rms jitter, −67 dBc fractional spur, and −58 dBc reference spur. With the proposed schemes, the fractional and reference spurs are suppressed by 29 and 32 dB, respectively.