Total Tester/PKG/Chip circuit-modeling methodology for predicting highly precise CDM breakdown voltage

CDM test is a reliability test performed before mass production to ensure Electro-Static Discharge (ESD) reliability. For smooth shipments of products, it is important to predict a breakdown voltage of the device on CDM test. We developed a new methodology to estimate the breakdown voltage accurately in the early phase of Chip or PKG design. First, we prepared special circuit models by dividing the CDM test system into three components: Tester, PKG, and Chip. We finally made each of these models that could reproduce the discharge current of the actual measurement. By using the models, we predicted the applied voltage to the target device such as MOSFET. By using the voltage, we made it possible to predict breakdown voltages based on our own standard. We achieved good agreement between the estimated breakdown voltage using our model and the experimental one. The difference was only approximately 7%. The results proved that our proposed methodology was correct. Furthermore, a series of these simulations are based on JEITA standard, and we are currently considering predicting breakdown voltages in accordance with JEDEC standard. By using the derived Tester model based on JEDEC standard, the discharge current waveforms were in close agreement between the actual measurements and the simulations. At the end of the paper, we offer a simple calculation method of charged capacitance and prediction of the peak value of a discharge current. Furthermore, we provide an example of applying the results to the CDM verification for full Chip.