Tunneling Transistor With a Stacked Floating Electrode for Current Saturation

We demonstrated a tunneling transistor with a stacked floating electrode structure. Tunneling transistors suffer from a poor gate modulation property with large gate leakage current, absence of current saturation, and lithography limitations for a small tunneling gap. In this work, a floating electrode stacked vertically on source/drain electrodes was suggested to overcome these issues. The electric potential of the floating electrode was controlled by the side dual gate structure. Because of the vertical electron movement through the floating structure, ultra-small tunneling distance (~20 Å) can be easily obtained without a complicated lithography process. The operating voltage is thereby small (< 2 V) due to the thin tunneling barrier. The transistor also has a very low leakage current of ~10 pA due to the absence of electrode overlap. The gate modulation property was improved by controlling the potential energy level of the floating electrode. Additionally, the current saturation results were considerably enhanced. The average standard deviation is 15 nA/cm2 at the saturation region.