A Dynamic Current Balancing Method for Paralleled SiC MOSFETs With Gate-Branch Full-Coupled Inductors

In multichip SiC power modules, unbalanced dynamic currents between the paralleled dies can induce unbalanced switching losses and junction temperatures, reducing the device's lifetime. Existing current sharing methods face challenges of low integration or insufficient effectiveness. This article presents a highly integrated current balancing method with full-coupled inductors in the gate branches. Compared to existing methods, the presented method does not change the simple power circuit layout and the module area. Thus, it is easier to implement. Meanwhile, it can simultaneously suppress the unbalanced currents caused by the unbalanced parasitic self and mutual inductances, achieving balanced dynamic currents. A theoretical model is established to design the self-inductance values of the full-coupled inductors. The effectiveness of the method and the designed parameter value are well verified through simulations. Finally, experimental verifications are conducted. The test results show that the dynamic currents and switching losses in the optimized power module are well-balanced under different load currents and gate resistances. When R _g = 4.1 Ω and I _load(chip) = 56 A, the turn- on and turn- off current imbalance degrees are reduced from 50% and 20.6% to 3.5% and 4.1%, respectively. And the imbalance degree of the total switching losses is reduced by 72.3%.