相位裕度
偏移量(计算机科学)
CMOS芯片
带宽(计算)
放大器
电气工程
电子工程
电容器
电压
计算机科学
控制理论(社会学)
运算放大器
工程类
电信
控制(管理)
人工智能
程序设计语言
作者
Yanpeng Zhao,Haisong Li,Jinliang He,Lijun Gao,Zhu Shi,Bin Wang,Haikun Yue
标识
DOI:10.1109/itoec57671.2023.10292049
摘要
Based on the SMIC 65nm CMOS process, a high-speed continuous-time linear equalization (CTLE) with the proposed direct-current offset cancellation (DCOC) circuit is designed, error amplifier-capacitor filter and current adder are added basing on the traditional DCOC circuit, which improves offset cancellation ability under ensuring stability. Mean value of the offset voltage at output is suppressed to 17 μV with 1.1 mV standard deviation. Operating at 1.2V power supply, the design achieves 7 GHz bandwidth with 4.7 dB peak gain, 51 dB loop gain, 72 ° phase margin, -52 dB DC gain and 1.9 mW power consumption, DCOC circuit only contributes 0.1 mW.
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