A low-light-level CMOS image sensor with a novel correlated double sampling based on CTIA

This paper presents a low-light-level CMOS image sensor featuring a novel correlated double sampling (CDS) technique based on the capacitive transimpedance amplifier (CTIA) pixel circuit. In order to achieve high sensitivity for low-light-level imaging, we employ the CTIA pixel circuit with a small integration capacitor. To effectively eliminate pixel noise, we propose an innovative analog CDS structure based on the CTIA pixel, which utilizes only one capacitor for sampling and holding the reset signal within each pixel. By implementing this architecture in the column, we are able to perform subtraction between the reset signal and integration signal. As a result of this proposed CDS design, both pixel reset noise and part of the fixed-pattern noise (FPN) can be significantly reduced. We have fabricated a test chip using this method with a 128 × 128 pixel array in a standard 0.35 μm CMOS process. Experimental results demonstrate that our CIS employing the proposed CDS based on CTIA is capable of reducing temporal noise from 504.2μVrms to 213.6μVrms. Furthermore, at a frame rate of 5fps, our low-light-level CMOS image sensor equipped with this novel CDS technique is able to capture recognizable images even under illumination as low as 0.05lux.