薄脆饼
材料科学
互连
晶片键合
晶片测试
模具准备
集成电路
电子工程
光电子学
堆积
制作
晶片切割
晶圆规模集成
晶圆回磨
晶圆级封装
炸薯条
计算机科学
工程类
电气工程
化学
电信
有机化学
作者
Wei‐Chung Lo,Yuhua Chen,Jeng-Dar Ko,Tzu-Ying Kuo,Shih−Cheng Hu,Su-Tsai Lu
出处
期刊:Electronic Components and Technology Conference
日期:2006-07-10
被引量:3
标识
DOI:10.1109/ectc.2006.1645679
摘要
Abundant three-dimensional packaging technologies were developed for chip-to-wafer or wafer-to-wafer bonding, which employed through silicon interconnect to achieve the shortest circuit design of inter-chip or inter-wafer. In this paper, we focused on the wafer stacking technology by introducing silicon-through three-dimensional interconnect. The innovative structure as shown here is a new concept of three-dimensional integration of via-preformed silicon through wafers. Compared to the recently research of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated of wafer stacking using this reliable design. The wafer/chip thickness used here was 150 /spl mu/m and down to 50 /spl mu/m. The result shows the benefits of this structure can provide more reliable wafer stacking without any voids. Not only the assembly accuracy of the joint between two chips/wafers can be reduced, but we can get improvement of the yield of the whole wafer during the wafer bonding process, even the thickness uniformity of the wafer is higher than 10%. The experiment confirmed that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module.
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