覆盖
薄脆饼
计算机科学
钥匙(锁)
平版印刷术
过程(计算)
产品(数学)
节点(物理)
多重图案
半导体器件制造
特征(语言学)
分布式计算
可靠性工程
材料科学
抵抗
工程类
纳米技术
光电子学
程序设计语言
几何学
图层(电子)
哲学
操作系统
结构工程
语言学
计算机安全
数学
作者
Jigang Ma,Miao Yu,Cees Lambregts,Sotirios Tsiachris,Paul Böcker,Jun-Yeob Kim,Won-Kwang Ma,Sangjun Han,Chanha Park,Kyong-Seok Kim,Junghwan Kim,Sang-Jun Park,Gwang-Gon Kim
摘要
In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The on-product overlay budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer-to-wafer variation. Due to the complexity, a holistic methodology is used to combine various alignment solutions to achieve the optimal on-product overlay performance. In this paper, we evaluated the holistic method by simulation and experiment for DUV layers. We illustrate the expected on-product overlay improvement.
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