A 5–13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process

A 5-13.5 Gbps multi-standard I/O link receiver is presented in this paper. An inductor-free CTLE, whose gain and bandwidth are highly adjustable, is achieved by using the second-order negative capacitance circuit. A high jitter tolerance clock and data recovery (HJTOL-CDR) is proposed for Spread Spectrum Clock applications. In this work, the JTOL is improved by two ways: first, a partial-noise-shaping-based digital loop filter (PNS-DLF) is implemented to reduce the output jitter caused by the truncation error in the integral path; second, the proposed CDR logic is fully custom designed to operate at a quarter-rate clock of 5 GHz. Moreover, the CDR bandwidth can be tuned to satisfy various data rates and jitter masks. Post-layout simulation shows that the proposed CTLE can provide wide gain tuning range, the boost gain at 10 GHz is beyond 29 dB and the proposed CDR can tolerate up to 31-kppm frequency offset. The proposed receiver is fabricated in 40-nm CMOS with an active area of 0.06 mm ² and 65 mW power consumption at 20 Gbps from 1.2-V supply. Measurement results show that, when receiving the PRBS31 data at 10 Gbps with 5-kppm frequency offset across a channel with 14-dB loss, the JTOL is 0.39 UIpp at 10 MHz and can guarantee a 0.34 UIpp at high frequency, which proves that the proposed receiver can meet stringent standards such as PCIe 3.0/4.0, USB 3.2, DisplayPort 1.4.