A Review on the Key Optimization Techniques of SAR ADC Design

This paper mainly reviews some recent progress on successive approximation register (SAR) analog-to-digital converter (ADC) architectures with high speed and/or low power. Many studies aimed to optimize parameters of SAR ADCs: some enhanced energy efficiency and speed by capacitor-array circuit digital-to-analog convertor (CDAC) designing, some settled the problem of low speed and low signal-to-noise and distortion ratio (SNDR) by amplifier structuring. Certain articles overcame the mismatch of capacitors through calibration. Based on these, some further structures are raised.