Impact of Potential Barriers at Grain Boundaries of Multi Crystalline Silicon Wafers on Inductively Coupled Resistivity Measurements

Base resistance and emitter sheet resistance are two of the most important process control parameters in solar cell manufacturing, which may be measured inductively. On mono-crystalline silicon, measurement accuracy of this contactless inline technique has already been demonstrated. In this work the investigation of measurement accuracy is extended to multi-crystalline silicon (mc-Si) and reveals for base resistance measurements severe measurement artifacts of up to a factor 2 upon chemical standard treatments, such as damage etching and acidic texturization. The investigation identifies potential barriers at grain boundaries as reason for these artifacts which form upon chemical treatments and further increase with storage time after such chemical steps. It is found that these potential barriers vanish almost completely after thermal treatments, such as a standard emitter diffusion. As a consequence, the emitter sheet resistance calculated from the inductive sheet resistances before and after emitter diffusion may be significantly underestimated if the presumed base resistance is overestimated. Taking into account that mc-Si wafers are almost not affected by potential barriers in the as-cut state, we develop a patented procedure which allows reliable emitter sheet resistance measurements in mc-Si wafers irrespective of the presence of potential barriers before diffusion.