ATPG scan logic failure analysis: a case study of logic ICs – fault isolation, defect mechanism identification and yield improvement

Yield analysis of sub-micro devices has become an ever-increasing challenge. Scan based design is a powerful concept on complex designs that is routinely employed for fault isolation. To minimize the list of defect candidates according to fault diagnosis, precise failure localization with the help of failure analysis tool is needed as a complement. This example comes from a 0.13-um technology with six layers of copper interconnect. The chip has 18 scan chains with up to 2800 flip flops in each chain. Low Automatic Test Pattern Generation (ATPG) scan chain yield was reported during final scan test. This work presents the case study illustrating the application of scan diagnosis flow as an effective means to achieve yield enhancement.