Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

Abstract This paper presents a recent process for bottom gate‐controlled low‐temperature polysilicon (LTPS) TFT technologies for reliable low‐power high‐performance AMOLED displays. The experimental and physics‐based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. The process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates‐based device structures, is explored in conjunction with improved poly crystallization and poly‐Si/gate‐oxide interface by reducing defect density‐of‐state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance, such as optimal sub‐threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate experimental results in fabricated TFTs and gain more physical insight into the bottom‐gate LTPS device configuration to enable reliable low‐power high‐performance AMOLED display applications.