SEM ADI on device overlay: the advantages and outcome

The advanced logic node is continuously shrinking toward sub-nm node and EUV lithography is the one of main drivers to reach better patterning resolution resulting in reduced process steps. Along with this design rule shrink, On Product Overlay (OPO) requirement has been critical to the device yield making the accuracy and stability of optical overlay measurement to become primary concern on the lithography process control. Historically Optical Microscope (OM) ADI overlay was accepted and the standard for control to meet OPO requirements. Along the past years, as OPO budget diminishes with node-to-node, OM overlay required additional supporting reference data to compensate the inherent accuracy problem. Industry adopted the accuracy correction knob with High Voltage SEM (HV-SEM) at post etch, also known as SEM AEI overlay. The SEM AEI overlay measures the error contribution of different process influence and the overlay mark to real device pattern overly bias together. The inaccuracy of OM ADI overlay has been treated as a non-correctable error components till the on-device overlay measurement of HV-SEM after etching was enabled to compensate the delta known as Non-Zero Offset (NZO) or Mis-Reading Correction (MRC). Today the HV-SEM on-device overlay measurement at AEI is widely adopted as one of critical component to meet the OPO requirement enabling scaling for all types of advanced CMOS devices production. The main driver of On-Device-Overlay (ODO) measurement at AEI step is the see-through imaging capability to see all relevant layers through the stack even though the measurement step/time differs on the same wafer of the ADI optical overlay measurement are ranging from few to two-digit days depending on the process complexity. There has been an increasing need for a faster response of overlay measurements to close the overlay control loop and breakdown the device to target error versus the process overly induce component – in other words, to correct in the right step. This leads to the necessity of SEM ADI overlay measurement. With the recent e-Beam evolution of more higher landing energy, probe current and improved Total Measurement Uncertainty (TMU) performance, SEM ADI overlay measurement is enabled and considered to show the performances to meet market requirements on the selected layers of interest. In this paper, we would like to demonstrate the enablement of SEM ADI overlay measurement including the accuracy comparison with OM ADI overlay on the DBO scribe target versus real device pattern measurement performance. With SEM ADI and AEI overlay measurement on the same patterns, we could also demonstrate the error breakdown between optical target to device and from ADI to AEI process induced error which will enable the better correctable methodology to minimize NZO/MRC. In addition, this process contribution to error breakdown could be extended to improve, in the future, the Edge Placement Error (EPE) control.