A Precise Wafer Thinning Integration Process for nano-TSV Formation

This paper proposes the use of a Silicon-On-Insulator (SOI) substrate to control the final Si thickness on the substrate. After direct wafer-to-wafer bonding to another Si carrier wafer, a combination of grinding and etching is used to remove the Si substrate of the SOI wafer to expose the underlying BOX layer. Selective wet-etch process is then employed to remove the buried oxide (BOX) to stop on the thin SOI layer. Due to good wet etch selectivity between the BOX (oxide) and SOI Si, the remaining SOI Si thickness can be very well-controlled. In this paper, 175nm of remaining Si can be demonstrated on the bonded SOI wafer using this method. This method can be easily extended to even thinner final Si layers beyond 100nm. Nano-Tsvs with dimension of 300nm diameter and 500nm depth are then fabricated on the thinned SOI which is bonded to another carrier wafer.