A Low-Noise Area-Efficient Column-Parallel ADC With an Input Triplet for a 120-dB High Dynamic Range CMOS Image Sensor

This article presents and demonstrates the design of a high dynamic range (HDR) CMOS image sensor (CIS). Detailed operation of various comparator circuits is analyzed. A low-noise, area-efficient, wide-input range comparator is proposed for HDR applications. Based on the analysis, a six-transistor (6T) comparator is proposed with a p-type metal oxide semiconductor (PMOS) input triplet, which effectively increases the input range of a conventional PMOS-input type comparator and compensates the charge injection and kT/C noise introduced from pixels switching between high-conversion-gain (HCG) and low-conversion-gain (LCG) modes. The proposed scheme achieves an extra high dynamic range (DR). A full HD ( $1920\times1080$ ) HDR image sensor with $2.9 ~\mu \text{m}$ pixel pitches is fabricated in a 55 nm one-ploy five-metal (1P5M) CIS process. The incorporated analog-to-digital conversion (ADC) demonstrates a 12-bit resolution, a noise of $96 ~\mu _{\mathrm {VRMS}}$ , a power consumption of $25 ~\mu \text{W}$ , an area of $2.9\times 400\,\,\mu \text{m}$ , and its integral non-linearity (INL) and differential non-linearity (DNL) are −0.43/+7.22 and −0.30/+0.29 LSB, respectively. The sensor achieves a 120-dB DR at 30 frames/sec and a temporal noise of 0.91e-.