物理
发射机
计算机科学
干扰(通信)
频道(广播)
电子工程
无线
计算机网络
电信
物理层
工程类
作者
Junhan Bae,Myeongkyu Song,Byung Chul Kim,Junkyu Lee,Woosung Park,Jung-Hoon Chun
标识
DOI:10.1109/a-sscc56115.2022.9980792
摘要
This paper describes a MIPI C/D-PHY combo transmitter (TX) fabricated in 110nm CMOS image sensor (CIS) process. The same hardware can be shared to support both C-PHY and D-PHY with little extra circuitry. The adopted 32-bit architecture that enables double data rate (DDR) in C/D-PHY can maximize the data rate, allowing it to exceed the limits of legacy sub-micron process technologies. In addition, the proposed TX utilizes 3-tap feed-forward equalization (FFE) in both the C-PHY and D-PHY modes, effectively eliminating the inter-symbol interference (ISI) induced by band-limited channels. The measured results indicate that the compliance test verified in C-PHY mode is comfortably passed at data rates up to 11.4 Gbps (5 Gsps) per lane. The eye diagrams in D-PHY mode are fully open at the data rates up to 6 Gbps per lane.
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