A 11.4-Gbps/lane MIPI 32-bit C-PHY and D-PHY combo transmitter with 3-tap FFE

This paper describes a MIPI C/D-PHY combo transmitter (TX) fabricated in 110nm CMOS image sensor (CIS) process. The same hardware can be shared to support both C-PHY and D-PHY with little extra circuitry. The adopted 32-bit architecture that enables double data rate (DDR) in C/D-PHY can maximize the data rate, allowing it to exceed the limits of legacy sub-micron process technologies. In addition, the proposed TX utilizes 3-tap feed-forward equalization (FFE) in both the C-PHY and D-PHY modes, effectively eliminating the inter-symbol interference (ISI) induced by band-limited channels. The measured results indicate that the compliance test verified in C-PHY mode is comfortably passed at data rates up to 11.4 Gbps (5 Gsps) per lane. The eye diagrams in D-PHY mode are fully open at the data rates up to 6 Gbps per lane.