比较器
共模信号
磁滞
CMOS芯片
电压
晶体管
比较器应用
模式(计算机接口)
工艺角
电子工程
电气工程
噪音(视频)
控制理论(社会学)
计算机科学
物理
工程类
传输(电信)
控制(管理)
人工智能
图像(数学)
操作系统
量子力学
模拟信号
标识
DOI:10.1109/iccs56666.2022.9936471
摘要
In order to improve the ability of hysteresis comparators to suppress noise and interference signals and expand their common mode operating range, an improved hysteresis comparator circuit is proposed based on the analysis of the relationship between input common mode range, the tail current and the flip voltage, utilizing the common mode signal to realize adaptive bias of tail current transistor. Using SMIC 0.18$\mu$m 1P6M CMOS technology, the simulation results show that when supply voltage is 1.8V, 2.2V and 2.8V respectively, the proposed hysteresis comparator can work normally under the input common mode voltage changes from 0 to 1.5V at five process corners (TT, SS, FF, FS and SF).
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