Power Semiconductor Die Passivation Layer Stress Mechanism Investigation and optimization by Numerical Analysis

As the frontiers of power semiconductor package are constantly driven higher, faster voltage switching is associated with extreme thermal variation, which can cause package individual components to behave differently to each other, and potentially create substantial thermomechanical stress between them. A comprehensive assessment of such stress reliability of the brittle or ductile thin layers is necessary to enable higher performance products complying with industrial standard of wider application scenarios.Present study discusses Thermal Cycling Test (TCT) stress formation mechanism and optimization direction for power package both from package level design that includes clip topologies and Epoxy Molding Compound (EMC) properties, and from die structure level polyimide layer application. With ANSYS Workbench simulation tool, passivation layer stress distributions are obtained and compared with their deformation feature as well as with package bending trend during TCT. Stress concentration mechanisms and optimization directions can be revealed from those mapping relations. optimized package design and die structure design that follow stress relief mechanisms are proposed and numerically evaluated. Thereby designed experiment provides validation for both simulation results and stress concentration/mitigation mechanisms.