Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution

This article comprehensively analyzes the effects of differential capacitor array mismatches on the decision levels of charge-redistribution-based successive-approximation-register (SAR) analog-to-digital converters (ADCs), reveals the intrinsic relation between the differential CDAC mismatches and the output code distribution of SAR, and proposes a bit-weight calibration (BWC) algorithm for SAR in terms of raw output codes, which does not require any modification to the original design. The proposed BWC is applicable to other architectures that incorporate a SAR as a substage, such as a pipelined SAR (P-SAR). Physical measurement results are presented for a pure SAR and simulation results are presented for a two-stage P-SAR, both of which verified the theoretical analyses and the proposed calibration method.