Monolithically Integrated Logic Circuits Based on p-NiO Gated E-Mode GaN HEMTs

High-performance GaN based one-chip direct coupled field-effect-transistor logic (DCFL) circuits were demonstrated, in which enhancement-mode (E-mode) GaN high electron mobility transistors (HEMTs) were formed simultaneously with depletion-mode (D-mode) components through the selective-area growth of p-NiO gates at room temperature by sputtering. The process boasts advantages such as a low thermal budget cost, eliminating the need for high-temperature regrowth of p-GaN, and preventing dry-etch damage. The E-mode HEMT showcases a high current density of 1.3 A/mm, a positive threshold voltage of 0.83 V, and an ON-OFF current ratio of ${7}.{24}\times {10} ^{{8}}$ , which enable input/output logic level matching with a low drive/load ratio of 1.0. The E/D-mode inverter exhibits substantial logic-low and logic-high noise margins of 2.09 V and 2.45 V, respectively, a logic voltage swing of 4.78 V, a switching threshold of 2.45 V and a voltage gain of 42 at a supply voltage of 5.0 V. With the demonstrated capability to drive power switches, this architecture provides an elegant solution for high-frequency power switching applications.