A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces

This article presents a 24 Gb/s/pin single-ended capacitively driven transceiver that employs four-level pulse amplitude modulation (PAM-4), tailored for high-density die-to-die (D2D) interfaces. To fulfill the high-throughput demand in D2D interfaces, a PAM-based crosstalk cancellation (XTC) technique capable of improving the channel density is proposed along with a doubled per-pin data rate using PAM-4 signaling. Remarkably, the proposed XTC technique only requires a single capacitor at the output node for crosstalk compensation, thereby minimizing bandwidth (BW) degradation by reducing parasitic components. The transmitters leverage a proposed thermometer-weighted driver architecture, characterized by its high energy efficiency and linearity, to facilitate PAM-4 signaling within the capacitively driven link. Additionally, a true-single-ended time-based decoding technique is proposed for the PAM-4 receiver to alleviate both hardware and design complexities. Fabricated using a 28 nm CMOS process, the proposed transceivers exhibit a power consumption of 11 mW at a data rate of 24 Gb/s/pin, resulting in an energy efficiency of 0.458 pJ/bit.