Scaling physically aware logic diagnosis to complex high volume 7nm server processors

Logic diagnosis attempts to identify defects within a microprocessor using only a logical model of the design with no knowledge of the physical layout. Physically aware logic diagnostics greatly improves callout resolution, enabling diagnosis of new fault types, but presents scalability issues for large, complex processor designs. This paper highlights solutions needed to create an efficient high-volume physical diagnosis pipeline. Results of the proposed system are demonstrated on 7nm processor designs.