Power efficient charge pump in deep submicron standard cmos technology

A power-efficient charge pump is proposed. The use of low-voltage transistors and of a simple two-phase clocking scheme permits the use of higher operating frequencies compared to conventional solutions, thus obtaining high current, high efficiency, and small area. Measurements show good results for frequencies around 100 MHz. Two test patterns have been fabricated, one with three stages and one with five stages, in a 1.8-V 0.18-μm triple-well standard CMOS digital process (six metals). High-voltage capacitors have been implemented using metal to metal parasitic capacitance.