A 1.23W/mm2 83.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns

For more efficient power management in processors, a high-frequency and multi-phase (MP) integrated voltage regulator (IVR) using multiple inductors would be an ideal solution to deliver optimized power with rapid dynamic voltage scaling (DVS) [1]–[5]. Nevertheless, in practical use, MP-IVRs suffer from an inter-inductor current imbalance because of mismatches in integrated inductances, different parasitic resistances, and duty-control skews among all phases (top of Fig. 18.1.1). Such a current mismatch may cause larger output ripple and efficiency degradation, losing the benefits of multi-phase operation. Also, thermal hotspots can occur due to excessive current density and deteriorate reliability. Previous approaches [2], [4] use current sensors to calibrate the duty cycle of each phase, but the design complexity and power overhead tend to be greatly increased in the high-speed sensing circuitry for fast-switching converters. An additional consideration in MP-IVRs is the phase-shedding technique, which can improve the light-load efficiency by reducing the number of phases. In many prior works [1], [2], the number of phases was adjusted by 2N (e.g., 1-2-4) for simplicity of phase division. If the phase-shedding is more fine-grained, the overall efficiency can be more flattened over a wide range of loads. Moreover, because the frequency response and output ripple vary according to the number of phases, the MP-IVR should be adaptively optimized further for them. This paper presents a 400MHz 6-phase fully integrated buck converter (bottom of Fig. 18.1.1). Key contributions of this work include 1) inter-inductor true-average-current matching by the flying-capacitor-based peak-and-valley differential sensing (PVDS) technique with near-zero power overhead, 2) area-efficient dynamic re-allocation of on-chip capacitors used either in the PVDS or at the output for optimizing responsiveness and voltage ripple adaptively to the number of phases, and 3) DLL -based multi-phase clock generation (MPCG) for fine-grained phase-shedding functionality, improving efficiency over a wide load range.