锁相环
抖动
相位噪声
算法
采样(信号处理)
线性
计算机科学
数学
物理
电子工程
电信
工程类
探测器
作者
Wanghua Wu,Chunhua Yao,Kunal Godbole,Ronghua Ni,Pei-Yuan Chiang,Yongping Han,Yongrong Zuo,Ashutosh Verma,Ivan Siu-Chuang Lu,Sang Won Son,Thomas Byunghak Cho
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2019-05-01
卷期号:54 (5): 1254-1265
被引量:97
标识
DOI:10.1109/jssc.2019.2899726
摘要
An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting $2 \times 2$ multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm 2 .
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