A novel silicon heterojunction IBC process flow using partial etching of doped a‐Si:H to switch from hole contact to electron contact in situ with efficiencies close to 23%

Abstract We present a novel process sequence to simplify the rear‐side patterning of the silicon heterojunction interdigitated back contact (HJ IBC) cells. In this approach, interdigitated strips of a‐Si:H (i/p + ) hole contact and a‐Si:H (i/n + ) electron contact are achieved by partially etching a blanket a‐Si:H (i/p + ) stack through an SiO x hard mask to remove only the p + a‐Si:H layer and replace it with an n + a‐Si:H layer, thereby switching from a hole contact to an electron contact in situ , without having to remove the entire passivation. This eliminates the ex situ wet clean after dry etching and also prevents re‐exposure of the crystalline silicon surface during rear‐side processing. Using a well‐controlled process, high‐quality passivation is maintained throughout the rear‐side process sequence leading to high open‐circuit voltages (V OC ). A slightly higher contact resistance at the electron contact leads to a slightly higher fill factor (FF) loss due to series resistance for cells from the partial etch route, but the FF loss due to J 02 ‐type recombination is lower, compared with reference cells. As a result, the best cell from the partial etch route has an efficiency of 22.9% and a V OC of 729 mV, nearly identical to the best reference cell, demonstrating that the developed partial etch process can be successfully implemented to achieve cell performance comparable with reference, but with a simpler, cheaper, and faster process sequence.