纳米电子学
材料科学
薄脆饼
纳米技术
工程物理
工程类
作者
Alain Phommahaxay,Gerald Beyer,Iuliana Radu,Eric Beyne,Alice Guerrero,Luke Prenger,Kim Yess,Kim Arnold,Sebastian Tussing,W. Spieß,Thomas Rapps,Koen Kennes,Stefan Lutter,Arnita Podpod,Steven Brems,John Slabbekoorn,Erik Sleeckx,Cedric Huyghebaert,Inge Asselberghs,Miller Andy
标识
DOI:10.23919/iwlpc.2019.8914124
摘要
Thin substrate handling has become one of the cornerstone technologies that enabled the development of 3D stacked ICs over the past years. Temporary wafer bonding has continuously improved and reached the maturity level required by volume manufacturing of first-generation devices. Yet the need remains for further development and performance increases. Indeed, the continuous push for denser interconnects has brought new requirements for a through-silicon-via technology on one side but also pushed temporary adhesive and carrier technology into the space of wafer reconstruction and fan-out WLP. On the opposite side of the semiconductor spectrum, at the early steps of the front-end-of-line processing, transistor scaling becomes more and more challenging, including demanding the integration of higher numbers of novel materials. To further increase the options of materials, a growing number of exploratory devices are considering using a layer transfer approach. The advances in temporary bonding and debonding technology is bringing the packaging and nanoscale world together.
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