n‐Type Dirac‐Source Field‐Effect Transistors Based on a Graphene/Carbon Nanotube Heterojunction

Abstract As a type of steep‐slope transistor, a Dirac‐source field‐effect transistor (DS‐FET) provides both high performance and sub‐60 mV dec −1 subthreshold swing (SS) at room temperature. However, only p‐type DS‐FETs are experimentally demonstrated, and n‐type DS‐FETs for constructing complementary metal–oxide–semiconductor (CMOS) logic circuits are lacking. Here, the first experimental demonstrations of n‐type DS‐FETs and tunneling FETs (TFETs) based on a graphene/carbon nanotube heterojunction with a Sc drain are provided. The as‐fabricated n‐type DS‐FETs present a minimum SS as low as 37 mV dec −1 at room temperature and a high I 60 of 2.6 µA µm −1 ( V ds = 0.1 V), which reflect an advantage in the on‐state performance of more than two orders of magnitude over the TFETs. In addition, the G m / I ds ratio reaches 70 V −1 , which breaks the physical limit (38.5 V −1 ) and reflects the ultrahigh transconductance efficiency of the transistor for analog applications. The realization of n‐type DS‐FETs not only opens a door to achieving CMOS DS‐FETs for future high‐energy‐efficiency digital electronics and high‐performance analog electronics but also further verifies the validity and universality of device physics for DS‐FETs.