中间层
晶圆级封装
模具准备
晶片测试
过程(计算)
炸薯条
薄脆饼
制造工程
集成电路封装
材料科学
模具
包装工业
计算机科学
光学(聚焦)
包装工程
球栅阵列
工程类
扇出
造型(装饰)
晶圆规模集成
电信
电气工程
纳米技术
图层(电子)
晶片切割
蚀刻(微加工)
物理
光学
复合材料
操作系统
出处
期刊:International Conference on Electronics Packaging
日期:2016-04-01
被引量:11
标识
DOI:10.1109/icep.2016.7486819
摘要
Industry interest in fan-out wafer level packaging has been increasing steadily. This is partially because of the potential behind panel-based fan-out packaging, and partially because wafer level packaging may be fulfilling needs not met by interposer-based and 3D technologies. As is the case with any technology, there are variations within the fan-out wafer level packaging category. This paper will focus on two of the primary processes: RDL-first and mold-first (also called chip-first). While these process flows have many of the same activities, those activities are carried out in a different order, and there are a few key steps that will differ. Each process has unique challenges and benefits, and these will be explored and analyzed.
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